System Verilog Assertion - SVA - All the ones on the data bus should be contiguous

SystemVerilog
,
4

In reply to verification_engineer_smart:

 
// Untested, but it looks OK
   bit[15:0] q; 
  function automatic bit contig (bit[15:0] x);
      bit gota1;
      for (int i=0; i<16; i++) begin 
        if(!gota1 && x[i]==1'b1) gota1=1'b1;
        else if(gota1 && x[i]==1'b0 ) return 0; 
        else if(i==15 && (!gota1 || x[i]==1'b1)) return 1; 
      end
   endfunction

   property p_contig; 
    bit[15:0] v;
     @ (posedge clk) $rose(a) |-> (1, v=contig(q))  ##0 v;  
   endproperty 
   ap_contig: assert property(@ (posedge clk) p_contig);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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