System Verilog Assertion - SVA - All the ones on the data bus should be contiguous

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

In reply to verification_engineer_smart:
Provide an example for your requirements. Also is this for all cycles or do you have an antecedent?


bus 1011110001101   //  pass or fail? 
011111100001010 // ? 
Other           // PASS 
Other           // FAIL

101111001101 //fail
000111100000 //pass
000000011111 //pass
000000110001 //fail