System Verilog Assertion - SVA - All the ones on the data bus should be contiguous

SystemVerilog
,
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In reply to ben@SystemVerilog.us:

This is a model with lots of debug info.


// import sva_delay_repeat_range_pkg::*;
module top; 
  timeunit 1ns/100ps;
  `include "uvm_macros.svh"
   import uvm_pkg::*;
   bit clk, a; 
   bit[15:0] q; 
   function automatic bit contig (bit[15:0] x);
      bit gota1, gota10;
      $display("%t x= %h", $realtime, x);
      for (int i=15; i>=0; i--) begin 
         if(i!=0 && !gota1 && !gota10 && x[i]==1'b1) begin 
            $display("i=%d  (i!=0 && !gota1 && !gota10 && x[i]==1'b1 gota1", i); gota1=1'b1; end // new '1'
         if(i!=0 && !gota1 && !gota10 && x[i]==1'b0) begin 
            $display("i=%d  (i!=0 && !gota1 && !gota10 && x[i]==1'b0 bull", i);  end // there was a 1, new 0
         if(i!=0 && gota1 && x[i]==1'b0) gota10=1'b1; // there was a 1, new 0
         if(gota10 && x[i]==1'b1) begin 
            $display("gota10 && x[i]==1'b1 return 0"); return 0; end // was a 10, now new 1 -> error 
         if(i==0 && !gota10)  begin 
            $display("i==0 && !gota10) return 1"); return 1; end // last bit, no 10-> OK, no error  
         if(i==0 && x[i]==1'b1) 
            begin $display("i==0 && x[i]==1'b1) return 0"); return 0; end // was a 10, now new 1 -> error 
         if(i==0 && x[i]==1'b0) begin 
            $display("i==0 && x[i]==1'b0) return 1"); return 1; end // was a 10, now new 0 -> OK 
        /*case ({i==0, gota10, gota1})
         3'b000: if(x[i]==1'b1) gota1=1'b1;  // new '1'
         3'b001: if(x[i]==1'b0) gota10=1'b1; // there was a 1, new 0
         3'b01x: if(x[i]==1'b1) return 0; // was a 10, now new 1 -> error 
         //3'b011: if(x[i]==1'b1) return 0; // was a 10, now new 1 -> error 
         3'b10x: return 1; // last bit, no 10-> OK, no error 
         //3'b101: return 1; // was a 1, NO 10, x==0000000...10 or x==000000...11-> OK 
         3'b11x: if(x[i]==1'b1) return 0; // was a 10, now new 1 -> error 
                 else return 1; // was a 10, now new 0 -> OK 
         //3'b111: if(x[i]==1'b1) return 0; // was a 10, now new 1 -> error 
         //       else return 1; // was a 10, now new 0 -> OK 
          
        endcase*/
      end
   endfunction

   property p_contig; 
    bit v;
     @ (posedge clk)  (1, v=contig(q), $display("v=%b", v))  ##0 v;  
     // $rose(a) |-> (1, v=contig(q))  ##0 v;  
   endproperty 
   ap_contig: assert property(@ (posedge clk) p_contig) $display("%t PASS q=%h", $realtime, $sampled(q));
                           else $display("%t FAIL q=%h", $realtime,  $sampled(q));  

   
 // when bit "a" is high then at the next cycle 
   // bit [1:0]b ==11 ##1 b==00 ##1  b=11... Continuous, 
  // suppose in between a=0 then again whenever 'a' becomes 1 then b value is 11 and then continuous same as above??

     
   initial forever #10 clk=!clk;  
  
     initial begin 
       repeat(20) begin 
           @(posedge clk);   
           if (!randomize(q, a)  with // a dist {1'b1:=1, 1'b0:=1};
           { q dist {16'b0000111100000000:=1, 16'b0000111100011000:=1}; 
       }) `uvm_error("MYERR", "This is a randomize error");
       end 
       $finish; 
      end  
endmodule

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
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** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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