System Verilog Assertion - SVA - All the ones on the data bus should be contiguous

SystemVerilog
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In reply to verification_engineer_smart:

You need to understand the evaluation regions in Svg.
See SVA evaluation - SystemVerilog - Verification Academy

(1, v=contig(q)) ##0 v;
Am using a sequence_match item; the 1 forces the variable v to be equal to the result of the function call. I then continue the evaluation of the consequent. If v==0, then the sequence is a no match and assertion fails.
Ben systemverilog.us