System Verilog Assertion - SVA - All the ones on the data bus should be contiguous

SystemVerilog
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In reply to ben@SystemVerilog.us:

Ben

In the property, can “a” be “clk”?

Also, can you please explain this property, in some detail :

@ (posedge clk) $rose(a) |-> (1, v=contig(q)) ##0 v;

Thanks