System verilog assertion on asynchronous signals

SystemVerilog
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In reply to ben@SystemVerilog.us:

Hi Ben ,

Thanks for replying , I understand that your solution accounts for the pulse rejection when dat is changing from no-check to check , but the other case is it changing from check to no-check which is the second red marker the image.
How can I handle that case ? May be I misunderstood you answer .

Thanks