I read a coding guideline that always@* is used for modelling combinational logic alone(includes latches as well). But my doubt is whether verilog/systemverilog compilers accept the usage of always@* for modelling sequential logic as well.
For instance lets consider that following code
always @(posedge clk)
begin
out <= in;
end
always @(*) //is this allowed or will it be errored out?(ie will it infer clk as a trigger for the always block)
begin
@(posedge clk);
out = in;
end
After synthesis will the two be identical ie will they both involve flops?
Any pointers (documents or webpages) on “in general, how to predict the post synthesis hardware logic just by seeing the RTL code” would be appreciated.
Thanks for the Help!
There is no longer a standard for synthesizable (System)Verilog, so it’s up to the synthesis tool vendors to do whatever they want. However I can say with reasonable certainty that every synthesis tool will error-out on your second always block.
Do a search on rtl synthesis guidelines for verilog. From from https://www.idc-online.com/technical_references/pdfs/electronic_engineering/RTL_Coding_for_Logic_Synthesis.pdf 1.2.8. Blocking vs non-blocking-race condition
• Never mix a description of combinational (blocking) construct with sequential (nonblocking).
• Blocking: combinational racing
Since the final outputs depends on the order in which the assignments are evaluated, blocking
assignments within sequential block may cause race condition.
• Nonblocking: sequential No race condition
Nonblockng assignments closely resemble hardware as they are order independent.