SVA to check if there is any glitch in the signal between two toggles of the same signal

SystemVerilog
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1

property acs_3k9_frq_check_5b;
@(posedge o_c_500k) disable iff(!o_acs_en)
$rose(o_c_3k9)|-> if(i_c_3k9_freq == 2’b00) delay_seq(32) |-> $rose(o_c_3k9)
else if (i_c_3k9_freq == 2’b01)delay_seq(64) |-> $rose(o_c_3k9)
else if (i_c_3k9_freq == 2’b10)delay_seq(128) |-> $rose(o_c_3k9)
else if (i_c_3k9_freq == 2’b11)delay_seq(256) |-> $rose(o_c_3k9);
endproperty
Above is my assertion to check from one rising edge of o_c_3k9 signal to another rising edge of the same signal to be either 32, 64, 128, 256 o_c_500k clk signal. I’m using the delay_seq provided by the BEN. This assertion is to check the number of o_c_500k clock cycles constitute one o_c_3k9 cycle. This assertion perfectly works.

But my query is, I need to check if there is any unwanted multiple toggles of o_c_3k9(excluding the usual high to low toggle during the half cycle and low to high at the full cycle.). This is to check if there is any glitch in between two toggles.The assertion should fail if there is any unnecessary toggles. I tried some assertions but didn’t work. Please help me to resolve this.

Regards,
Nandeesh

2

In reply to Nandeesha:

I would use an always @ (o_c_3k9) and using a
local variable in the always block, calculate if the pulse widths are within limits for the expected range, as defined by i_c_3k9_freq
Ben systemverilog.us