SVA: throughout vs until

SystemVerilog
, ,
9

In reply to ben@SystemVerilog.us:

ap_untilw: assert property(
	$rose(a) |-> b until_with c ##1 !b) 
	 $display("ap_untilw passed, b=%b at %t", $sampled(b), $time);  	
 
	ap_until_eq: assert property($rose(a) |-> b[*1:$] ##0 c ##1 !b) ; // equivalent assertion

In the above example, there is no clock referred for the property. Will it not get any compilation issue?