In reply to moogyd:
Thanks a lot Ben!
The observed behavior makes more sense now. Although it also shows that I only have quite a superficial understanding of SVA :-(
Steven
p.s. Just out of interest, the example https://www.edaplayground.com/x/39YH behaves differently with Incisive and Riviera Pro. There are different messages in the log.
The different messages is because Riviera displays all messages, vacuous and non-vacuous, whereas Incisive displays only the non-vacuous passes. There should be a switch for Riviera to suppress the vacuous pass action blocks.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115