In reply to dmitryl:
It is illegal. Note:
valid_l ##0 v_d=data_l;
is illegal because property local variable must be written in sequence_match_item
The following is your only choice.
property p_dldr;
bit[15:0] v_d;
@(posedge clk) (valid_l, v_d=data_l) |-> ##[1:UPPER] valid_r ##0 data_r==v_d;
endproperty
Putting the local variable in the sequence does not make that variable visible to the property.
The local variable can be declared in the property and passed as an argument to the sequence.
But, it really is too much bother, and makes the code less readable.
Ben SystemVerilog.sv