[SVA] Sequence of data

SystemVerilog
, , ,
5

In reply to ben@SystemVerilog.us:

Could the following


property p_dldr; 
bit[15:0] v_d; 
@(posedge clk) (valid_l, v_d=data_l) |-> ##[1:UPPER] valid_r ##0 data_r==v_d;
endproperty

be re-written as:


sequence vld_seq;
  @(posedge clk) 
  valid_l ##0 v_d=data_l;
endsequence

property p_dldr; 
bit[15:0] v_d; 
@(posedge clk) vld_seq |-> ##[1:UPPER] valid_r ##0 data_r==v_d;
endproperty

?