In reply to dmitryl:
You’re correct, I missed the valid_r.
@(posedge clk) (valid_l, v_d=data_l) |->
##[1:UPPER] valid_r ##0 data_r==v_d; // Corrected
A sequence can be one of the following:
sequence_expr ::= // See 1800::16.7
…
( sequence_expr {, sequence_match_item } ) [ sequence_abbrev ]
sequence_match_item ::=
operator_assignment
| inc_or_dec_expression
| subroutine_call
sequence_abbrev ::= consecutive_repetition
consecutive_repetition ::=
[* const_or_range_expression ]
| [*]
| [+]
Ben SystemVerilog.us