In reply to CPU_Verif:
The solution explained in the book is incorrect because it does not meet the following requirement:
“Making sure that bmode is not high while oe and dack are high”
What it does instead is:
“Making sure that bmode is not high for 2 cycles and then when oe and dack are high”
Below are my untested changes
//Solution explained using throught
sequence data transfer; // 6 cycles in length
##2 ((dack ==1) && (oe==1))[*4];
//After 2 cycles the oe and dack are high for 4 cycles continuous
endsequence
sequence checkbmode;
(!bmode) throughout data_transfer;
//Making sure that bmode is not high for 2 cycles and then when oe and dack are high
endsequence
//Making sure that bmode is not high for 2 cycles and then when oe and dack are high
@(posedge clk) $fell(bmode) |-> checkbmode;
endproperty
//Making sure that bmode is not high only when oe and dack are high
// In other words, (dack==1 && oe==1 && !bmode)[*4];
property pbrule1a; // simplified to
@(posedge clk) $fell(bmode) |-> ##2 (dack==1 && oe==1 && !bmode)[*4];
endproperty
property pbrule1b;
@(posedge clk) $fell(bmode) |-> ##2
(dack ==1 && oe==1[*4] intersect !bmode[*4]);
endproperty
//Making sure that bmode is not high for 2 cycles and then when oe and dack are high
endsequence
property pbrule1c;
@(posedge clk) $fell(bmode) |-> (##2 dack==1 && oe==1[*4]) intersect !bmode[*6]; // 6 cycles total
endproperty
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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