I’m trying to write an assertion to check the value of a signal ladder_value when FSM is in the below two states. This works but fails to repeat throughout the simulation. I want to have an assertion that keeps checking for the FSM to go to those two states and check for the value of the ladder_valu…

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SVA for FSM

SystemVerilog

nimitz_class July 8, 2021, 12:09am 3

In reply to warnerrs:

I need some signal before fsm to use implication, right?