IMPORTANT NOTICE:
Please be advised that the Verification Academy Forums will be offline for scheduled maintenance on Sunday, April 6th at 2:00 US/Pacific.
Verification Academy
SVA for FSM
SystemVerilog
FSM
,
assert-property
,
SVA-for-FSM
,
SVA
,
SystemVerilog
warnerrs
July 7, 2021, 11:47pm
2
In reply to
nimitz_class
:
Why are you using s_eventually instead of an implication?
show post in topic