SVA Covered and Uncovered properties in coverage report

SystemVerilog
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1

“…/Assertions/switch_assertions.sv”, 46: top.DUT.sva.CHECK_INPUT_INTF6: Antecedent of the implication never satisfied.
“…/Assertions/switch_assertions.sv”, 83: top.DUT.sva.CHECK_MEM_INTF1: started at 90ns not finished
“…/Assertions/switch_assertions.sv”, 90: top.DUT.sva.CHECK_MEM_INTF4: started at 117470ns not finished

I am trying to cover the property mentioned at line 46.However it is uncovered as per the coverage report. But I can see it in the waveform. What can be the reason ?

Also,property mentioned at line 83 isnt covered but the rest of the properties which arent finished are covered(for example-property mentioned at line no 90 is covered)?

Kindly guide.I am new to SVA.

2

In reply to MP_12:

Cannot possibly help you with this without seeing any code. What is it you see in the waveform?

3

In reply to dave_59:

On Antecedent of the implication never satisfied, t line 46.However it is uncovered as per the coverage report. But I can see it in the waveform.:
The cause for the lack of coverage may be that not all possibilities of the antecedent were a match. For example,


  a ##[1:$] b ##1 c |->  d; 
a ##[1:$] b ##1 c has an infinite number of possibilities.

Ben