SVA(BEN PAPER REFERENCE 2018) CONTINUE

SystemVerilog
1

Hi Ben,

Thanks for the reply

I want to ask the requirement of assertion as follows:

1:Upon a rose of all idles, we should check for that they remain high for dynamic number of clockedges which is defined by variable logic [7:0] dynamic .
2.if this condition passes we will check for variable clockgate/clock_en to be zero…
2. if it fails at any clock edge suppose dynamic clock edge value is 14 and one of the idles toggle to zero,the assertion shoul fail at the next clockedge no moving forward.

3.clockgate variable is directly related to clock_en that is if clock_en goes low it goes low immediately

code tried
sequence sq_rpt_simple_count(sq, count);
int v=count;
(1, v=count) ##0 ( v>0 ##0 sq, v=v-1) [1:$] ##0 v<=0;
endsequence // sq_rpt_simple_count
module m;
import sva_delay_repeat_range_pkg::;
bit clk, a, b, c, d, e, w;
int duration;

sequence q_abcde; @(posedge clk) a && b && c && d && e; endsequence
assert property(@(posedge clk)
q_abcde ##0 sq_rpt_simple_count(q_abcde,duration) |-> q_abcde ##1 clk_en==0;
endmodule

This code is working fine ,but it doesn’t catch the error which it should suppose all idles are not high during the whole duration of dynamic variable ,but it catches after the certain number of clock edge and requirement is to comes out immediately if either of a,b,c,d,e is not high representing idle or clock_en suddenly goes low in the period when all a,b,c,d,e are high.

Request you to add a control to catch to catch a scenario if either of a,b,c,d,e which are idle goes low after going to high.it should stop immediately and also in the mean time check for clock_enable to be zeroif either of condition happens it should show error.

so variable a,b,c,d,e are all idles

clock_en and clockgated signals are related to each other directly as clock_en goes low it goes low .

for more reference I have tried your two questions

2

In reply to bhajanpreetsinght:

For simplicity, I’ll use 2 idles and a static delay. This will give you the concepts.

  • 1:Upon a rose of all idles, we should check for that they remain high for dynamic number of clockedges which is defined by variable logic [7:0] dynamic .


$rose(A)[->1] and $rose(B)[->1] |-> (A && B)[*3] // the *3 is after both have risen
  • 2.if this condition passes we will check for variable clockgate/clock_en to be zero…

$rose(A)[->1] and $rose(B)[->1]  |-> (A && B)[*3] ##1 ck_en==0 // fails if consequent is a no match
$rose(A)[->1] and $rose(B)[->1]  |-> sq_rpt_simple_count(q_abcde,duration) ##1 ck_en==0;
// Dynamic repeat instead of [*3]
  • 2B. if it fails at any clock edge suppose dynamic clock edge value is 14 and one of the idles toggle to zero,the assertion shoul fail at the next clockedge no moving forward.
$rose(A)[->1] and $rose(B)[->1] |-> (A && B)[*3] ##1 ck_en==0;

q_abcde ##0 sq_rpt_simple_count(q_abcde,duration) |-> q_abcde ##1 clk_en==0;
fails if the A && B ==0 or if after the repeat passes, ck_en==1.

  • 3.clockgate variable is directly related to clock_en that is if clock_en goes low it goes low immediately

Now tune the above to your needs.
I can provide the concepts, but the detailed solutions should come from users.
Ben

3

In reply to ben@SystemVerilog.us:

Hi Ben,

suppose Idle it not 1 bit variable but two bit variable how to check it rose edge
suppose [1:0] a,[1:0] b;

can I write
$rose(A)[->1] and $rose(B)[->1] |-> (A && B)[*3] ##1 ck_en==0;

please comment

4

In reply to ben@SystemVerilog.us:

Hi Ben,

I have tried both ways.

$rose(A)[->1] and $rose(!$stable(B[1:0])) |-> (A && B)[*3] ##1 ck_en==0;

$rose(A)[->1] && $rose(!$stable(B[1:0]))|-> (A && B)[*3] ##1 ck_en==0;

it shows syntax error for both

5

In reply to bhajanpreetsinght:

In reply to ben@SystemVerilog.us:
suppose Idle it not 1 bit variable but two bit variable how to check it rose edge
suppose [1:0] a,[1:0] b;
can I write
$rose(A)[->1] and $rose(B)[->1] |-> (A && B)[*3] ##1 ck_en==0;
please comment

It depends on your understanding of the requirements.
Question to you: Having a good understanding of VG or SVG,

  1. what is the meaning of the vector “a” being true?
  2. What is the meaning of a rising to true?
    The answers should help with your questions.
6

In reply to bhajanpreetsinght:

Wrong basic answers on both items. May I suggest that you study SVG. There are many books on the subject, but for these specific 2 questions above, 1800’2017 is a good start.
Ben

7

In reply to ben@SystemVerilog.us:

Thanks Ben,

For letting me know that the answer are incorrect request you to suggest a way where multibit variable can be checked as the above requirement .Request you to please provide why the above example is showing syntax error.

8

In reply to bhajanpreetsinght:

I would recommend considering the possibility of collaborating with a colleague or seeking guidance from your teacher (if you are still in school) to enhance your understanding of Verilog code and SVA properties. It appears that there might be room for improvement in these areas based on your questions. If you are genuinely interested in pursuing a career in design and verification, it would be beneficial to invest time in studying and grasping the fundamentals of these disciplines. However, if this field doesn’t align with your interests, it might be worth exploring other career options that resonate with you more.
Ben

9

In reply to ben@SystemVerilog.us:

Hi Ben,

I always look upto learning and firmly believe that failing can make you learn new things.I always look upto you as mentor and have immense respect for your work .
I will go through as you told Ben ,but I would like to humbly request you to please shower your valuable advice in the above scenarios I know for vector $rose will not work so took reference from one of the answer how to make it work.

I would request you to please provide your valuable advice as it always work in my case as you guided me a multiple times only a hint would do

$rose(A)[->1] and $rose(!$stable(B[1:0])) |-> (A && B)[*3] ##1 ck_en==0;

$rose(A)[->1] && $rose(!$stable(B[1:0]))|-> (A && B)[*3] ##1 ck_en==0;

. Request you to please help sir