SVA(BEN PAPER REFERENCE 2018) CONTINUE

SystemVerilog
4

In reply to ben@SystemVerilog.us:

Hi Ben,

I have tried both ways.

$rose(A)[->1] and $rose(!$stable(B[1:0])) |-> (A && B)[*3] ##1 ck_en==0;

$rose(A)[->1] && $rose(!$stable(B[1:0]))|-> (A && B)[*3] ##1 ck_en==0;

it shows syntax error for both