In reply to dave_59:
In reply to muneebullashariff:
The bind construct is useful when inserting functionality inside your DUT without modifying your DUT when not practical. This is typically used by monitors and checkers as part of your testbench.
I don’t understood your second question. The bind construct connects to existing signals in your design. You can add whatever signals you want inside the interface.
Hey Dave,
Many thanks for your reply.
Let me explain my question: “If I need to add any interface signal during the simulation, is it possible to do using this bind concept?”
What I mean is, if my interface is as below before simulation starts:
interface int_if ( input logic clk,
input logic data_in,
input logic rst,
output logic data_o
);
endinterface : int_if
Can I add another input signal, say, logic a_in to the interface in any of the uvm_phases, is it possible to do it?
Thank you,
Regards,
Muneeb Ulla Shariff