SV bind in UVM where a parameter is used

When you use bind, all the identifiers you reference in the instantiation are from the target’s perspective, that includes the parameter override.


module flop
 #(parameter width = 1)
 (input wire [width-1:0] d,
 input wire clk,
 input wire rst_n,
 output wire [width-1:0] q
 );
endmodule : flop

module top;

   typedef logic [7:0]  uint8_t;
   typedef logic [15:0] uint16_t;
   logic 		clk, rst_n;
   uint8_t              d8,q8;
   uint16_t             d16, q16;
   
   flop #(8)  u8(.clk, .rst_n, .d(d8), .q(q8));
   flop #(16) u16(.clk, .rst_n, .d(d16), .q(q16));
   bind flop 
     meta_flop_metastability_injector_if #(.WIDTH(width)) i0 (
						      .meta_ff_d (d),
						      .dst_clk (clk),
						      .dst_rst_n (rst_n),
						      .meta_ff_q (q)
						      ); 
endmodule : top
		 
interface meta_flop_metastability_injector_if 
  #(parameter WIDTH = 1)(
			 input logic [WIDTH-1:0]  meta_ff_d, 
			 input logic 		  dst_clk,
			 input logic 		  dst_rst_n,
			 output logic [WIDTH-1:0] meta_ff_q
			 );
   initial $display("hello from %m WIDTH: %0d",WIDTH);

endinterface : meta_flop_metastability_injector_if