SV assertion for clock gating & Reset check

SystemVerilog
21

In reply to nimitz_class:

(!g_clk || g_clk) is equal to true (same as true or false.

22

In reply to ben@SystemVerilog.us:

In reply to nimitz_class:
(!g_clk || g_clk) is equal to true (same as true or false.

Yes, so in my case, I will not know whether the clock will be tied to 1 or 0 when clock enable is low. So, can I write the assertion this way?

23

In reply to nimitz_class:
The assertion does not make sense with your changes


property clk_gating_check_g_clk;
  @(posedge ref_clk)  //   ----------------       ----------------
   ($fell(clk_en) ##[2:4] (!g_clk || g_clk)) |-> ((!g_clk || g_clk) throughout clk_en[->1]);
endproperty	 
// IS SAME AS 
property clk_V2gating_check_g_clk;
  @(posedge ref_clk)
   ($fell(clk_en) ##[2:4] 1'b1 ) |-> (1'b1 throughout clk_en[->1]); // <<<----****
endproperty
// Above has 3 threads, and all 3 property threads  have to be true for the assertion to be succeed. 
// I don't think the assertion makes any sense