SV assertion for clock gating & Reset check

SystemVerilog
20

Can we do this if we don’t know what the clock will be tied to when enable is 0? I mean, g_clk can be 1 or 0 when enable is 0.

property clk_gating_check_g_clk;
		@(posedge ref_clk)
			($fell(clk_en) ##[2:4] (!g_clk || g_clk)) |-> ((!g_clk || g_clk) throughout clk_en[->1]);
	endproperty		
    ap_clk_gating_check_g_clk: assert property(clk_gating_check_g_clk);