Specifying constraints with implication operator

SystemVerilog
1

This is a simple constraint. Based on type of packet (ETHERNET/VLAN), I need to set the size of PayLoad array, which is sparse. I 'm able to realize the desired functionality using if-else which is not very elegant, as below.

constraint basic { if (PacketType == ETHERNET)
Payload.size > 17;
Payload.size < 1500;
else
if (PacketType == VLAN)
Payload.size > 30;
Payload.size < 1510;
else
------

How can I implement using implication operator:

The implementation below doesn’t work

constraint basic {
( PacketType == ETHERNET ) → { Payload.size > 17 && Payload.size < 1500 };
( PacketType == VLAN ) → { Payload.size > 30 && Payload.size < 1510 };
}

What is the difference between operator => and → in constraint space. LRM doesn’t talk abt “->” in constraints domain.

2

=> is not a valid implication operator for constraints, the syntax for constraints is different from the syntax for assertions.

The two constraint specifications are not the same. In the version using implication operators there is a two way implication going on - i.e. payload.size will determine which PacketType is selected, as well as the other way round.

If you add the constraint solve PacketType before Payload.size; then you will get behaviour consistent with the if-else constraint definition.

3

LRM doesn’t talk abt “->” in constraints domain.

I am not sure if I am missing something here but the LRM I am referring to has:

The implication operator ( –> ) can be used to declare an expression that implies a constraint

under random constraints section

Also I think your constraint look perfectly fine to me if we ignore the probability for ETHERNET and VLAN

4

In reply to manishp.p18:

The difference in a property is that A->B is overlapping implication (A implies B at the same time) while A=>B is non overlapping (A implies B follows the next cycle). Constraints are not temporal, so only → is allowed. An if constraint is the same as an implication, just different syntax.

When you say your constraint doesn’t work, you need to be explicit about what is happening. Are your solutions valid, but not getting what you wanted? Then as was posted, you need to work on the distributions.

5

Hi Dave,

I am trying to write constraint as follows:


class pkt;
  rand bit [3:0] addr;
  string addr_range;
  constraint range{if (addr_range=="small") addr<8 else if (addr_range == "large") addr inside {[8:30]} else addr > 100;}
endclass

module if_el_con;
initial
  begin
    pkt obj;
    obj = new();

repeat(7)
   begin
      obj.randomize;
     $display("pkt_1=%0d\n",obj.addr);
   end

obj.addr_range ="small";
   repeat(7)
   begin
      obj.randomize;
     $display("pkt=%0d\n",obj.addr);
   end
obj.addr_range= "large";
 $display("Large\n");
  repeat(7)
   begin
      obj.randomize;
     $display("pkt_large=%0d\n",obj.addr);
   end



  end
endmodule

but its giving error in else part is there any other way to write

Thanks

6

In reply to shobhana.swarnkar18:

It is good practice to indent your code properly. There were some curly braces and semi-colons missing.

constraint range{
    if (addr_range=="small") {
      addr<8;
    } else if (addr_range == "large") {
      addr inside {[8:30]};
  }else {
    addr > 100;
  }
}
7

In reply to sharvil111:

Thanks sharvil for the solution,I will take care the points mentioned next time.