Specifying constraints with implication operator

SystemVerilog
6

In reply to shobhana.swarnkar18:

It is good practice to indent your code properly. There were some curly braces and semi-colons missing.

constraint range{
    if (addr_range=="small") {
      addr<8;
    } else if (addr_range == "large") {
      addr inside {[8:30]};
  }else {
    addr > 100;
  }
}