Specifying constraints with implication operator

SystemVerilog
5

Hi Dave,

I am trying to write constraint as follows:


class pkt;
  rand bit [3:0] addr;
  string addr_range;
  constraint range{if (addr_range=="small") addr<8 else if (addr_range == "large") addr inside {[8:30]} else addr > 100;}
endclass

module if_el_con;
initial
  begin
    pkt obj;
    obj = new();

repeat(7)
   begin
      obj.randomize;
     $display("pkt_1=%0d\n",obj.addr);
   end

obj.addr_range ="small";
   repeat(7)
   begin
      obj.randomize;
     $display("pkt=%0d\n",obj.addr);
   end
obj.addr_range= "large";
 $display("Large\n");
  repeat(7)
   begin
      obj.randomize;
     $display("pkt_large=%0d\n",obj.addr);
   end



  end
endmodule

but its giving error in else part is there any other way to write

Thanks