Shortint and int is creating Difference

SystemVerilog
,
1

/* elements of the array to sum up to <1000*/
-------------------------------------Working

class tb;
rand int unsigned  a[10];
constraint aa{a.sum()<10'd1000;}
endclass

module rb;
tb A;
initial
begin
A=new();
repeat(10)
begin
A.randomize();
$display("%p",A.a);
end
end
endmodule

Result
'{'h0, 'h0, 'h5f, 'h1c, 'h0, 'h0, 'h0, 'h0, 'h0, 'h0}
'{'h0, 'h0, 'h2, 'h0, 'h221, 'h0, 'h0, 'h0, 'h0, 'h1be}
'{'he, 'h0, 'h2f, 'h0, 'hf, 'h0, 'h0, 'h14a, 'h0, 'h0}
'{'h17, 'h0, 'h1e2, 'h0, 'h9e, 'h54, 'h2, 'h33, 'h5, 'h0}
'{'h0, 'h0, 'h20e, 'h0, 'h3, 'h1f, 'h0, 'h0, 'h0, 'h0}
'{'h0, 'h0, 'h1b6, 'h0, 'hb1, 'h0, 'hb3, 'h0, 'h0, 'h0}
'{'h0, 'h270, 'h3, 'h0, 'h0, 'h0, 'h0, 'h116, 'h0, 'h29}
'{'h1, 'h21, 'h0, 'h0, 'h8e, 'h0, 'h0, 'h8, 'h0, 'h213}
'{'h0, 'h0, 'h5, 'h0, 'h0, 'h17, 'h0, 'h0, 'h0, 'h2b7}
'{'h0, 'h0, 'h3, 'h3, 'h8, 'h0, 'hda, 'h9, 'h244, 'h0}

-------------------------------------Not Working

class tb;
rand shortint unsigned  a[10];
constraint aa{a.sum()<10'd1000;} //if 'd is removed its working as desired
endclass

module rb;
tb A;
initial
begin
A=new();
repeat(10)
begin
A.randomize();
$display("%p",A.a);
end
end
endmodule

Result
'{'h2, 'h0, 'h83, 'h6, 'h2af, 'h0, 'h0, 'h0, 'h2, 'h40}
'{'h0, 'h0, 'h0, 'h0, 'h1f6, 'h1f, 'h0, 'h0, 'h0, 'h0}
'{'ha2, 'h6a, 'h0, 'h1, 'h9, 'h13, 'h68, 'h0, 'ha0, 'h1ac}
'{'h3, 'h0, 'h0, 'h1, 'h0, 'h289, 'h62, 'h38, 'h9c, 'h0}
'{'h0, 'h0, 'h1, 'h0, 'h11d, 'h0, 'h0, 'h11b, 'h0, 'h0}
'{'h0, 'h0, 'h0, 'h0, 'h0, 'h2e7, 'h0, 'h16, 'h0, 'h0}
'{'h56b, 'h1a21, 'h63, 'h39b, 'h691a, 'h8b4a, 'h2a0e, 'hb531, 'h265f, 'he454}
'{'ha754, 'hc443, 'h3e3b, 'he4c, 'h6f44, 'hb24c, 'h154f, 'h86, 'h11e9, 'h120}
'{'h7f7d, 'h3220, 'h192b, 'h77c2, 'h4ad0, 'hd9, 'h4b1f, 'h19d, 'h2f7, 'h250a}
'{'h0, 'h13a, 'h0, 'h63, 'h49, 'h0, 'h33, 'h42, 'h1a, 'h30}

For short int if 'd is removed its working as desired.
Resolve.
Thank you.

2

In reply to chashy:

The difference is that you did not run enough iterations or other tools to see that there is no difference—both example do not do always produce what you seem to expect. For example

'{'hffffffff, 'h5, 'h28, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h107}

is a valid solution top the first example. You always have to plan for overflow in Verilog expressions.

3

In reply to dave_59:

Hi Dave,
Could you please elaborate. When I changed shortint to int the results are constrained to as expected while having 'd included. For shortint 'd constraint is not working. Are you telling it is due to tool error?

class tb;
rand int unsigned a[10];
constraint aa{a.sum()<'d1000;}// this 'd while working with shortint
endclass
module rb;
tb A;
initial
begin
A=new();
repeat(10)
begin
A.randomize();
$display(“%p”,A.a);
end
end
endmodule
Result
'{'h0, 'h0, 'h5f, 'h1c, 'h0, 'h0, 'h0, 'h0, 'h0, 'h0}
'{'h0, 'h0, 'h2, 'h0, 'h221, 'h0, 'h0, 'h0, 'h0, 'h1be}
'{'he, 'h0, 'h2f, 'h0, 'hf, 'h0, 'h0, 'h14a, 'h0, 'h0}
'{'h17, 'h0, 'h1e2, 'h0, 'h9e, 'h54, 'h2, 'h33, 'h5, 'h0}
'{'h0, 'h0, 'h20e, 'h0, 'h3, 'h1f, 'h0, 'h0, 'h0, 'h0}
'{'h0, 'h0, 'h1b6, 'h0, 'hb1, 'h0, 'hb3, 'h0, 'h0, 'h0}
'{'h0, 'h270, 'h3, 'h0, 'h0, 'h0, 'h0, 'h116, 'h0, 'h29}
'{'h1, 'h21, 'h0, 'h0, 'h8e, 'h0, 'h0, 'h8, 'h0, 'h213}
'{'h0, 'h0, 'h5, 'h0, 'h0, 'h17, 'h0, 'h0, 'h0, 'h2b7}
'{'h0, 'h0, 'h3, 'h3, 'h8, 'h0, 'hda, 'h9, 'h244, 'h0}

4

In reply to chashy:

It would hep if you explained what “working” and “not working” means to you. The values you show meet the constraints you have given. You need to explain why you think the results are wrong.

Here is another way of looking at it.

module top;
  int unsigned aa32[10];
  shortint unsigned aa16[10];
  
  initial begin
    aa32 = {'hFFFFFFFF, 'h0, 'h0, 'h0, 'h0, 'h0, 'h0, 'h0, 'h0, 'h10};
    $display("Sum aa32 = %d",aa32.sum());
    if (aa32.sum()<10'd1000)
      $display("This is a valid random solution");
    else
      $display("This is an invalid random solution");
    
    aa16 = {'h56b, 'h1a21, 'h63, 'h39b, 'h691a, 'h8b4a, 'h2a0e, 'hb531, 'h265f, 'he454};
    
    $display("Sum aa16 = %d",aa16.sum());
    if (aa16.sum()<10'd1000)
      $display("This is a valid random solution");
      else
        $display("This is an invalid random solution");
  end
endmodule
5

In reply to chashy:

Please run the example I just provided, then try running it with a set of values you think violate your constraint. See this: A Little Verilog Knowledge Goes A Long Way in Understanding How SystemVerilog Constraints Work - Verification Horizons

6

Thanks Dave, the information provided was very much useful.