In reply to chashy:
The difference is that you did not run enough iterations or other tools to see that there is no difference—both example do not do always produce what you seem to expect. For example
'{'hffffffff, 'h5, 'h28, 'h0, 'h0, 'h0, 'h0, 'h1, 'h0, 'h107}
is a valid solution top the first example. You always have to plan for overflow in Verilog expressions.