Shortint and int is creating Difference

SystemVerilog
,
4

In reply to chashy:

It would hep if you explained what “working” and “not working” means to you. The values you show meet the constraints you have given. You need to explain why you think the results are wrong.

Here is another way of looking at it.

module top;
  int unsigned aa32[10];
  shortint unsigned aa16[10];
  
  initial begin
    aa32 = {'hFFFFFFFF, 'h0, 'h0, 'h0, 'h0, 'h0, 'h0, 'h0, 'h0, 'h10};
    $display("Sum aa32 = %d",aa32.sum());
    if (aa32.sum()<10'd1000)
      $display("This is a valid random solution");
    else
      $display("This is an invalid random solution");
    
    aa16 = {'h56b, 'h1a21, 'h63, 'h39b, 'h691a, 'h8b4a, 'h2a0e, 'hb531, 'h265f, 'he454};
    
    $display("Sum aa16 = %d",aa16.sum());
    if (aa16.sum()<10'd1000)
      $display("This is a valid random solution");
      else
        $display("This is an invalid random solution");
  end
endmodule