In reply to om30:
You cannot simply convert your SV code into UVM cide. The UVM has a certain structure and you have to follow this structure. The UVM testbench is constructed of agents. Each agent has inside a sequencer, a driver and a monitor (active agent). All these components are class-base. The UVM is heavily employing TLM. This requires working with seq_items. For simplifying the access to DUT regsietrs the UVM has a RAL which mirrors all your DUT registers in the testbench. These are only a very few aspects you have to consider.