Hi chr_sue,
The code which I had posted is a task in my interface of sv testbench code which now I am trying to convert into a UVM testbench code.
Here my requirement is that I want to do register read write operation for particular testcase so in my sv testbench I am providing addr and data to this task of interface and doing register read write operation but in UVM as I can’t drive anything from testcase I am planning to make a sequence of register read and register write which will be driven by driver so there won’t be any interface into my testcase of uvm.