Sequence in Sensitivity List

SystemVerilog
,
3

In reply to Have_A_Doubt:

I would say YES to both.
From 1800’2017:4.5 SystemVerilog simulation


execute_time_slot {
  execute_region (Preponed);
    execute_region (Pre-Active); 
      while (any region in [Active ... Pre-Postponed] is nonempty) {
          while (any region in [Active ... Post-Observed] is nonempty) {
             execute_region (Active);
             R = first nonempty region in [Active ... Post-Observed];
             if (R is nonempty)
                move events in R to the Active region; // **1**
          }
          while (any region in [Reactive ... Post-Re-NBA] is nonempty) {
            execute_region (Reactive);
            R = first nonempty region in [Reactive ... Post-Re-NBA];
            if (R is nonempty)
                move events in R to the Reactive region;
          }
          if (all regions in [Active ... Post-Re-NBA] are empty)
             execute_region (Pre-Postponed);
       }
       execute_region (Postponed);
}

With your code:

sequence  sr1;
    @( posedge clk ) req ##2 gnt ;
  endsequence
 
  always @( sr1 )   //  Doubt  regarding  the  triggering 
    $display(" TIME : %3t  Sequence  sr1  completes " , $time)

The @(posedge clk) start the time step. Within that time step you have all these regions.
In the Observed region sr1 is evaluated to be a match or no-match.
The algortithm says:
R = first nonempty region in [Active … Post-Observed];
if (R is nonempty)
move events in R to the Active region; // 1
In that Active region, in the loop-back, the event @(sr1) is true and the always @( sr1 ) is executed.
That’s how I see it.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
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