SBClock has 64 posedges/negedges followed by 32 UI of low

SystemVerilog
, ,
1

Hi Forum,
I have a SBClk of 800MHz which is used to sample data by the receiver.
The requirement is that ::
(1) There are 64 posedge/negedge of SBClk ( during which data is sampled )
(2) After 64th negedge, SBClk would remain low for min. 32 unit intervals
( 1 unit interval is (1/(800 x 10^6 Hz ) i.e 1.25ns. 32 UI would be 40ns )

So the sequence is (1) → (2) → (1) → (2) …

My attempts are as follows:

// For (1) ::
sequence s1;
   @(posedge sbclk) 1[*64] ;
endsequence
// However I don't want 's1' to execute for 2nd to 64th posedge as it would fail.

//  For (2)  capture time on 64th negedge
property p1;
 realtime t1;
 s1.triggered[->1] ##0 @(negedge sbclk)  (1,t1 = $realtime) |-> @(posedge sbclk) ( ($realtime-t1) >= 40ns ) ;
endproperty

[A] Any suggestion for (1) to ensure that the 64 posedges are checked only for the 1st attempt ( after intial SBClk low )

[B] Thoughts on (2) . Any possible limitations in (2) ?

2

Hi, I would introduce a virtual clock @800MHz keeping going while sbclk is low. Then you can use it for your properties/assertions…

3

ANother possibility:
[YOU]1 have a SBClk of 800MHz which is used to sample data by the receiver.
The requirement is that ::
(1) There are 64 posedge/negedge of SBClk ( during which data is sampled )
(2) After 64th negedge, SBClk would remain low for min. 32 unit intervals
( 1 unit interval is (1/(800 x 10^6 Hz ) i.e 1.25ns. 32 UI would be 40ns )

So the sequence is (1) → (2) → (1) → (2) …

// [A] Any suggestion for (1) to ensure that the 64 posedges are checked only for the 1st attempt
//( after intial SBClk low )

  // [Ben] Use support logic to lockmout other attempts 

bit lock; // enable a single thread 0f 64 clocks in the sequence, thus forcing one endpoint
function automatic void set_lock(bit x); lock=x; endfunction 
// For (1) ::
sequence s1;
   @(posedge sbclk) (lock==0, set_lock(1)) ##0 1[*64] ##0 (1,set_lock(0));
endsequence
// However I don't want 's1' to execute for 2nd to 64th posedge as it would fail.

//  For (2)  capture time on 64th negedge
property p1;
 realtime t1;
 @(posedge sbclk) s1.triggered ##0 @(negedge sbclk)  (1,t1 = $realtime) |-> @(posedge sbclk) ( ($realtime-t1) >= 40ns ) ;
endproperty

Ben Cohen Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.
https://systemverilog.us/vf/Cohen_Links_to_papers_books.pdf

4

Thanks Ben.
Adding an antecedent for (1) to avoid failure at 2nd to 64th posedge of sbclk

sequence s1;
  1[*64] ;  // Inherits clock
endsequence

 property p1;
  @(posedge sbclk) (lock==0, set_lock(1)) |-> s1 ##0 (1,set_lock(0));
 endproperty

//  For (2)  capture time on 64th negedge
property p1;
 realtime t1;
 @(posedge sbclk) s1.triggered ##0 @(negedge sbclk)  (1,t1 = $realtime) |-> @(posedge sbclk) ( ($realtime-t1) >= 40ns ) ;
endproperty
5 
//for the .triggered, you either neeed an explicit clock or a default clock
sequence s1;
  1[*64] ;  // Inherits clock
endsequence

 property p1;
  @(posedge sbclk) (lock==0, set_lock(1)) |-> s1 ##0 (1,set_lock(0));
 endproperty

// [YOU]
//  For (2)  capture time on 64th negedge
property p1;
 realtime t1;
 @(posedge sbclk) s1.triggered ##0 @(negedge sbclk)  (1,t1 = $realtime) |-> 
                    @(posedge sbclk) ( ($realtime-t1) >= 40ns ) ;
endproperty
// [Ben] If s1 had a clock, the way s1 is declared, after the very first 64th clocking event 
//       and from there on, s1.triggered is true at every clock
// THUS, p1 will not work. Go back to my original solution.

Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.

6 
// [Ben] If s1 had a clock, the way s1 is declared, after the very first 64th clocking event
//  and from there on, s1.triggered is true at every clock
// THUS, p1 will not work. Go back to my original solution.

Thanks Ben.

s1.triggered would be true on 65th posedge and each following posedge 66th , 67th , …
This would cause assertion to fail in cases where it would be essentially calculating time difference between 66th posedge and following negedge ( 67th negedge )

Also in my original post for (2) I had used go-to repetition operator for s1.triggered.
This would result in pass/fail report for earlier attempts ( from 1st posedge onwards )
As you pointed , (2) should be written without go-to repetition ::

//  For (2)  capture time on 64th negedge i.e negedge following 64th posedge // 
//  s1.triggered would be true on 64*n th posedge. For other posedges there would be a vacuous pass.
property p1;
 realtime t1;
 @(posedge sbclk) s1.triggered ##0 @(negedge sbclk)  (1,t1 = $realtime) |-> @(posedge sbclk) ( ($realtime-t1) >= 40ns ) ;
endproperty

I have one final question to conclude the thread.
As I mentioned at the top of this thread

I have a SBClk of 800MHz which is used to sample data by the receiver.
The requirement is that ::
(1) There are 64 posedge/negedge of SBClk ( during which data is sampled )
(2) After 64th negedge, SBClk would remain low for min. 32 unit intervals
( 1 unit interval is (1/(800 x 10^6 Hz ) i.e 1.25ns. 32 UI would be 40ns )
The sequence is (1) → (2) → (1) → (2) …

What are the possible checks ?
(a) SBCLK is low for 32 unit intervals ( 40ns )
(b) Time period of SBCLK is 1.25ns. Time period can be checked by noting time difference between 2 successive posedge / negedge. However care needs to be taken that time difference between the 64th posedge/negedge and the 65th posedge/negedge would be significantly high due to 32UI low in between.

[Q1] For (b) should I check for time difference between 2 successive posedge as well as 2 successive negedge ?
[Q2] Any other check possible other than (a) and (b) ? Should I check for duty cycle as well ?