Sampling inout ports from interface

SystemVerilog
1

I have an inout port in my dut i.e “sda”.I declared it as tri1 in interface .

I want to sample “sda”
how i can do that??

i am getting this error

Error-[XMRE] Cross-module reference resolution error
reciever.sv, 60
Error found while trying to resolve cross-module reference.
token ‘sda’. Originating package ‘pkg’.
Source info: this.sda <= intf_rec.cb.sda;

intf_rec is virtual interface , cb is clocking block

2

In reply to sameer.msa:

Show us the actual code declaring and referencing all names mentioned.

3

In reply to dave_59:

task reciever :: recv();


    if (on) $display ("%t ,%s,%m",$realtime,name);
begin 
  this.sda<=intf_rec.sda_pin;
        $display("from reciever recv task");
  this.reg_clk_out<=intf_rec.cb.reg_clk_out;
  $display ("sda=%d,reg_clk_out=%d",this.sda,this.reg_clk_out);
#5000;
  end

  endtask
4

In reply to sameer.msa:

I recieved data from reciever ,by changing inout port “sda” in interface from “tri1” to wire

5

In reply to sameer.msa:

We’re misssing a lot of context here; What is “this”? I know the keyword is meant for “this” class, but you’ve not told us at all about this class. We can infer it’s name is “receiver” from your external task definition, but no nothing more about class “receiver”.

And since you’re talking about port “sda” (I assume within an interface), I don’t think you want “this.sda”. You may want just “sda”. But again, more context would help us help you.

Regards,

Mark