Sampling inout ports from interface

SystemVerilog
3

In reply to dave_59:

task reciever :: recv();


    if (on) $display ("%t ,%s,%m",$realtime,name);
begin 
  this.sda<=intf_rec.sda_pin;
        $display("from reciever recv task");
  this.reg_clk_out<=intf_rec.cb.reg_clk_out;
  $display ("sda=%d,reg_clk_out=%d",this.sda,this.reg_clk_out);
#5000;
  end

  endtask