Same define use for multiple

SystemVerilog
,
1 
generate
for( genvar slice =0; slice <WRAPPER-1; slice++)begin
`active_rst_assert(m_reset[slice])
`active_rst_deassert(m_reset[slice],m_clk[slice])
end
endgenerate

xmvlog: E,SVNPSN (file.sv,**): The value in the single-bound form of a range must be positive.

I have used `define macros for the multi use of the property, wanted to use the same property(checking for the reset) for the multiple instances.

2

In reply to muku_383:

`define text macros get expanded before any SystemVerilog code gets parsed. Can you use your property directly with arguments?

3

In reply to muku_383:

Your issue , as dave said, is the argument m_reste[slice] since the macro is expanded before if gets evaluated. You should use a temp var to store it before and then assign. Regards

4

In reply to Rsignori92:

Without seeing the macro definition it’s impossible to suggest an alternative.

5

In reply to dave_59:


`define ah_rst_assert(val)\
 bit ``val``_tb;\
 always @(posedge ``val``_in)begin\
    //logic\
 end\
 property ss_``val``_in_assert_property;\
    // logic\
 endproperty\

//*****************************
`define trigger_assertions(val,assert_deassert)\
 ``val``_in_``assert_deassert``_check:assert property(ss_``val``_in_``assert_deassert``_property);\

`ah_rst_assert(ss_rst)

//*****************************
`trigger_assertions(ss_rst,assert)

//********************************
generate
for( genvar slice =0; slice <WRAPPER-1; slice++)begin
`active_rst_assert(m_reset[slice])
`active_rst_deassert(m_reset[slice],m_clk[slice])
end
endgenerate // error


//********************************

I hope this might help.

6

In reply to muku_383:

Not really helpful.

7

In reply to dave_59:

I will rewrite the complete code for you and share the EDA playground link.