Same define use for multiple

SystemVerilog
,
5

In reply to dave_59:


`define ah_rst_assert(val)\
 bit ``val``_tb;\
 always @(posedge ``val``_in)begin\
    //logic\
 end\
 property ss_``val``_in_assert_property;\
    // logic\
 endproperty\

//*****************************
`define trigger_assertions(val,assert_deassert)\
 ``val``_in_``assert_deassert``_check:assert property(ss_``val``_in_``assert_deassert``_property);\

`ah_rst_assert(ss_rst)

//*****************************
`trigger_assertions(ss_rst,assert)

//********************************
generate
for( genvar slice =0; slice <WRAPPER-1; slice++)begin
`active_rst_assert(m_reset[slice])
`active_rst_deassert(m_reset[slice],m_clk[slice])
end
endgenerate // error


//********************************

I hope this might help.