In reply to dave_59:
This is the error message I get :
** Error: G:/Verilog/uvm_ex1.sv(2): Could not find the package (uvm_pkg). Design read will continue, but expect a cascade of errors after this failure. Furthermore if you experience a vopt-7 error immediately before this error then please check the package names or the library search paths on the command line.
** Error: G:/Verilog/uvm_ex1.sv(3): Cannot open include file "uvm_macros.svh". ** Error: G:/Verilog/uvm_ex1.sv(5): (vlog-2163) Macro uvm_info is undefined.
** Error: G:/Verilog/uvm_ex1.sv(5): near “(”: syntax error, unexpected ‘(’