Regression randomization is failling

UVM
,
1

…>i am randomizing variable using constraint into the sequence class.where we are getting the plusargs value using config_db and i set the config_db into testbench.
1>> individual sim folder when i am doing simulation all the plusargs max and min values are coming and we are able to randomize in between max and min value.but

when coming for regression my plusargs values are not coming.
:-points i have observed.
1.i chacked the log file for both individual simulation and regression >>command we are passing both are same.
2> i give the max and min value into the regress.sh file and same mod_sparse . we are calling this into command line.
main problem is that
my plusargs values are printing zero.

thanks and regards
ashish kumar

2

In reply to Ashishkumar072:

You need to give more information. Verification engineers need to know how to break down problems into smaller steps and communicate effectively.

  • What is the difference between the individual runs and the regression ones? You say the commands are the same. Are they running from the same script? Compare the switches in the log files.
  • What simulator and regression system are you using?
  • How are you fetching the plusargs? Are you using the SystemVerilog methods or the UVM command line processor? Can you share the code? Better yet, can you break this code out into an example? The process of creating a test case often leads to discovering the real problem.
3

In reply to chrisspear:

module tb;
//variable decleration
bit [7:0] axi_awaddr_up_master_min;
bit [7:0] axi_awaddr_down_master_min;
bit [7:0] axi_awaddr_up_master_max;
bit [7:0] axi_awaddr_down_master_max;

//value plusargs
if($value$plusargs(“axi_awaddr_up_master_min”, axi_awaddr_up_master_min))
$display(“axi_awaddr_up_master_min=%0d”, axi_awaddr_up_master_min);
if($value$plusargs(“axi_awaddr_down_master_min”, axi_awaddr_down_master_min))
$display(“axi_awaddr_down_master_min=%0d”, axi_awaddr_down_master_min);
if($value$plusargs(“axi_awaddr_up_master_max”, axi_awaddr_up_master_max))
$display(“axi_awaddr_up_master_max=%0d”, axi_awaddr_up_master_max);
if($value$plusargs(“axi_awaddr_down_master_max”, axi_awaddr_down_master_max))
$display(“axi_awaddr_down_master_max=%0d”, axi_awaddr_down_master_max);
//configuration set
Uvm_config_db#(bit[7:0])::set(null,””,”axi_awaddr_up_master_min”,axi_awaddr_up_master_min);
Uvm_config_db#(bit [7:0])::set(null,””,”axi_awaddr_down_master_min”,axi_awaddr_down_master_min);
Uvm_config_db#(bit [7:0])::set(null,””,”axi_awaddr_up_master_max”,axi_awaddr_up_master_max);
Uvm_config_db#(bit [7:0])::set(null,””,”axi_awaddr_down_master_max”,axi_awaddr_down_master_max);
endmodule

//tansaction class
bit [7:0] axi_awaddr_up_master_min;
bit [7:0] axi_awaddr_down_master_min;
bit [7:0] axi_awaddr_up_master_max;
bit [7:0] axi_awaddr_down_master_max;
rand bit [127:0] addr;

constraint c{addr>axi_awaddr_up_master_min; addr>axi_awaddr_down_master_min; addr<axi_awaddr_up_master_max; addr<axi_awaddr_down_master_max;}
endclass
regress.sh file///hare we are assigning the man ,max value to the plusargs variable
axi_awaddr_up_master_min=2
axi_awaddr_down_master_min=2
axi_awaddr_up_master_max=4
axi_awaddr_down_master_max4

during the simulation run we are calling this file first
////////////////

//seq class
bit [7:0] local_axi_awaddr_up_master_min;
bit [7:0] local_axi_awaddr_down_master_min;
bit [7:0] local_axi_awaddr_up_master_max;
bit [7:0] local_axi_awaddr_down_master_max;
task body();
if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_up_master_min”local_axi_awaddr_up_master_min))
uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_up_master_min”)) if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_down_master_min”local_axi_awaddr_down_master_min)) uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_down_master_min”))
if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_up_master_max”local_axi_awaddr_up_master_max))
uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_up_master_max”)) if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_down_master_max”local_axi_awaddr_down_master_max)) uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_down_master_max”))

Assert(tx.randomizae() with {axi_awaddr_up_master_min==local_axi_awaddr_up_master_min; axi_awaddr_down_master_min==local_axi_awaddr_down_master_min; axi_awaddr_up_master_max==local_axi_awaddr_up_master_max; axi_awaddr_down_master_max==local_axi_awaddr_down_master_max;});

Endtask

…the diference b/w the simulation run and regression run
… >>i am using vivado 2022 simulator
simulation >we are simulating for gen5 and single lane with of pcie
but in regressing we are running for all generation and all devcombination at a time

the problem is that
for individual simulation it is working we are able to constraint it but in the regression its fails to constraint.

i have taken the print of that plusargs that vlaue is showing 0 means plusargs is not passing

4

In reply to Ashishkumar072:

Several issues. It looks like you cut & pasted through Word, which changed the quotes, and capitalized some words. I cleaned up your test case and created a small example. You had the wrong syntax for the $value$plusargs argument, so I fixed that too.

module tb;
  bit [7:0] axi_awaddr_up_master_min=255;

initial begin
  if ($value$plusargs("axi_awaddr_up_master_min=%d", axi_awaddr_up_master_min))
    $display("Arg found");
  else
    $display("Arg not found");
  $display("axi_awaddr_up_master_min=%0d", axi_awaddr_up_master_min);
end
endmodule

This runs on Questa Edit code - EDA Playground

You probably have a scripting issue that you need to debug. The plusarg is probably being lost or transformed in the bad simulation.

5

In reply to chrisspear:

thank you

thare is script issue now it is fixed.
thank you

6

In reply to Ashishkumar072:

OK, you asked the question, I suggested a solution, now what is the answer? These forums are for sharing knowledge, so help the next person by showing what was wrong and how you fixed it.