In reply to Ashishkumar072:
You need to give more information. Verification engineers need to know how to break down problems into smaller steps and communicate effectively.
- What is the difference between the individual runs and the regression ones? You say the commands are the same. Are they running from the same script? Compare the switches in the log files.
- What simulator and regression system are you using?
- How are you fetching the plusargs? Are you using the SystemVerilog methods or the UVM command line processor? Can you share the code? Better yet, can you break this code out into an example? The process of creating a test case often leads to discovering the real problem.