In reply to chrisspear:
module tb;
//variable decleration
bit [7:0] axi_awaddr_up_master_min;
bit [7:0] axi_awaddr_down_master_min;
bit [7:0] axi_awaddr_up_master_max;
bit [7:0] axi_awaddr_down_master_max;
//value plusargs
if($value$plusargs(“axi_awaddr_up_master_min”, axi_awaddr_up_master_min))
$display(“axi_awaddr_up_master_min=%0d”, axi_awaddr_up_master_min);
if($value$plusargs(“axi_awaddr_down_master_min”, axi_awaddr_down_master_min))
$display(“axi_awaddr_down_master_min=%0d”, axi_awaddr_down_master_min);
if($value$plusargs(“axi_awaddr_up_master_max”, axi_awaddr_up_master_max))
$display(“axi_awaddr_up_master_max=%0d”, axi_awaddr_up_master_max);
if($value$plusargs(“axi_awaddr_down_master_max”, axi_awaddr_down_master_max))
$display(“axi_awaddr_down_master_max=%0d”, axi_awaddr_down_master_max);
//configuration set
Uvm_config_db#(bit[7:0])::set(null,””,”axi_awaddr_up_master_min”,axi_awaddr_up_master_min);
Uvm_config_db#(bit [7:0])::set(null,””,”axi_awaddr_down_master_min”,axi_awaddr_down_master_min);
Uvm_config_db#(bit [7:0])::set(null,””,”axi_awaddr_up_master_max”,axi_awaddr_up_master_max);
Uvm_config_db#(bit [7:0])::set(null,””,”axi_awaddr_down_master_max”,axi_awaddr_down_master_max);
endmodule
//tansaction class
bit [7:0] axi_awaddr_up_master_min;
bit [7:0] axi_awaddr_down_master_min;
bit [7:0] axi_awaddr_up_master_max;
bit [7:0] axi_awaddr_down_master_max;
rand bit [127:0] addr;
constraint c{addr>axi_awaddr_up_master_min; addr>axi_awaddr_down_master_min; addr<axi_awaddr_up_master_max; addr<axi_awaddr_down_master_max;}
endclass
regress.sh file///hare we are assigning the man ,max value to the plusargs variable
axi_awaddr_up_master_min=2
axi_awaddr_down_master_min=2
axi_awaddr_up_master_max=4
axi_awaddr_down_master_max4
during the simulation run we are calling this file first
////////////////
//seq class
bit [7:0] local_axi_awaddr_up_master_min;
bit [7:0] local_axi_awaddr_down_master_min;
bit [7:0] local_axi_awaddr_up_master_max;
bit [7:0] local_axi_awaddr_down_master_max;
task body();
if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_up_master_min”local_axi_awaddr_up_master_min))
uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_up_master_min”)) if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_down_master_min”local_axi_awaddr_down_master_min)) uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_down_master_min”))
if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_up_master_max”local_axi_awaddr_up_master_max))
uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_up_master_max”)) if (!uvm_config_db# (bit [7:0])::get(null,” ”,”axi_awaddr_down_master_max”local_axi_awaddr_down_master_max)) uvm_fatel (get_type_name,$sformatf(“did not axi_awaddr_down_master_max”))
Assert(tx.randomizae() with {axi_awaddr_up_master_min==local_axi_awaddr_up_master_min; axi_awaddr_down_master_min==local_axi_awaddr_down_master_min; axi_awaddr_up_master_max==local_axi_awaddr_up_master_max; axi_awaddr_down_master_max==local_axi_awaddr_down_master_max;});
Endtask
…the diference b/w the simulation run and regression run
… >>i am using vivado 2022 simulator
simulation >we are simulating for gen5 and single lane with of pcie
but in regressing we are running for all generation and all devcombination at a time
the problem is that
for individual simulation it is working we are able to constraint it but in the regression its fails to constraint.
i have taken the print of that plusargs that vlaue is showing 0 means plusargs is not passing