Regarding assertion implementation

SystemVerilog
1
  1. Assertion for the delay implementation , the input data will be coming after delay12.5ps
    so I wanted to check that data , here delay is randomize and it is 9 bits i.e. [8:0]delay
    so while implementation
    property input_mode_idel;
    realtime t1=12.5
    @(posedge clk ) disable iff (disable || !gsrn || !por_n)
    (indel_a) |-> ##[delay    t1] (data==inff);
    endproperty

It is giving an error , as delay cannot take variables , is their any other way . Can you please suggest some other way to implement this ?

Thanks .

2

In reply to bijal:

Example:


module top; 
    timeunit 1ns;     timeprecision 100ps;  
    import uvm_pkg::*; `include "uvm_macros.svh" 
    import sva_delay_repeat_range_pkg::*;
    bit clk, a, b, c=1, w;  
    int d1=2, d2=5;  // <-- the delays variables 
    sequence q_s;
        a ##1 c; 
    endsequence   
    sequence my_sequence; 
        a ##1 w[->1]; 
    endsequence 
    default clocking @(posedge clk); 
    endclocking
    initial forever #10 clk=!clk;  
 
    // ******       DYNAMIC DELAY ##d1 **********
    // Application:  $rose(a)  |-> q_dynamic_delay(d1) ##0 my_sequence;
    ap_dyn_delay: assert property(@ (posedge clk) 
       $rose(a) |-> q_dynamic_delay(d1) ##0 my_sequence);

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers:
3

In reply to ben@SystemVerilog.us:

By using this package import sva_delay_repeat_range_pkg::;
delay is randomize at that particular when indel is 1 that value of delay should be multiplied by 12.5 ps in the interface class and after that data should be compared
(indel_a) |-> ##[delayt1] (data==inff);

4

In reply to bijal:

The package import sva_delay_repeat_range_pkg::*;
ERROR :- package could not be bound

5

In reply to bijal:

  • I don’t understand your requirements.
    indel is 1 that value of delay should be multiplied by 12.5 ps in the interface class and after that data should be compared
    (indel_a) |-> ##[delay    t1] (data==inff);* What does this 12.5ps have to do with the clocking event ? a new clocking event 12.ps later? If no, you need to create that event outside SVA with support logic and use multiclocking in SVA. If you are going to do all of that, you might as well use the fork/join_none approach to do verification; this is described in my paper Understanding the SVA Engine,
    Verification Horizons - July 2020 | Verification Academy
  • On ERROR :- package could not be bound, please show code

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…

  1. SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
  2. Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
    Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb
  3. Papers: