In reply to bijal:
- SVA is based on clocking events
- Delays and repeats have to be static multiple of the clocking event.
Thus, ##1.2 b is illegal; there is NO 1.2 clock periods; at least clocked registers don’t work that way. - For dynamic delays, you can use my SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
Example:
module top;
timeunit 1ns; timeprecision 100ps;
import uvm_pkg::*; `include "uvm_macros.svh"
import sva_delay_repeat_range_pkg::*;
bit clk, a, b, c=1, w;
int d1=2, d2=5; // <-- the delays variables
sequence q_s;
a ##1 c;
endsequence
sequence my_sequence;
a ##1 w[->1];
endsequence
default clocking @(posedge clk);
endclocking
initial forever #10 clk=!clk;
// ****** DYNAMIC DELAY ##d1 **********
// Application: $rose(a) |-> q_dynamic_delay(d1) ##0 my_sequence;
ap_dyn_delay: assert property(@ (posedge clk)
$rose(a) |-> q_dynamic_delay(d1) ##0 my_sequence);
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact http://cvcblr.com/home.html
** SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
…
- SVA Package: Dynamic and range delays and repeats SVA: Package for dynamic and range delays and repeats | Verification Academy
- Free books: Component Design by Example FREE BOOK: Component Design by Example … A Step-by-Step Process Using VHDL with UART as Vehicle | Verification Academy
Real Chip Design and Verification Using Verilog and VHDL($3) https://rb.gy/cwy7nb - Papers:
- Understanding the SVA Engine,
Verification Horizons - July 2020 | Verification Academy - SVA Alternative for Complex Assertions
Verification Horizons - March 2018 Issue | Verification Academy - SVA in a UVM Class-based Environment
SVA in a UVM Class-based Environment | Verification Horizons | Verification Academy