Random number generation without repetition

SystemVerilog
,
1

Dear team,

Kindly advise a few methods to generate random numbers within a specified range with examples

2

In reply to ArjunNag:
I’ll give you one way and you can explain why you need “a few”

module top;
class A;
  randc int number; // randc means do not repeat until all solutions produced
  int low_bound = 1, high_bound = 10;
  constraint c_range { number inside {[low_bound:high_bound]}; }
endclass

A a_h = new;
initial repeat (100) begin
           void'(a_h.randomize());
           $display(a_h.number);
      end
endmodule
3

In reply to dave_59:

Dear Dave,

below is the outcome of the above code…

kindly advise next steps

run: 15.20-s038: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
Top level design units:
top
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Loading snapshot worklib.top:sv … Done
SVSEED default: 1
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
ncsim> source /incisiv/15.20/tools/inca/files/ncsimrc
ncsim> run
0
0
0
0
0
0
0
…
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
Done

4

In reply to ArjunNag:
I had a small typo, call **a_h.**randomize()

5 
module top;
  
  class a;
    
   randc int num;
    int rang1=100;
    int rang2=200;
    constraint c{ num inside {[rang1:rang2]};}
  endclass
  
  a handle;
  
  initial
    begin
      handle =new();
      
      repeat(10)
        begin
          handle.randomize();
          $display("num=%d",handle.num);
        end
    end
      endmodule