Random number generation without repetition

SystemVerilog
,
2

In reply to ArjunNag:
I’ll give you one way and you can explain why you need “a few”

module top;
class A;
  randc int number; // randc means do not repeat until all solutions produced
  int low_bound = 1, high_bound = 10;
  constraint c_range { number inside {[low_bound:high_bound]}; }
endclass

A a_h = new;
initial repeat (100) begin
           void'(a_h.randomize());
           $display(a_h.number);
      end
endmodule