In reply to dave_59:
Dear Dave,
below is the outcome of the above code…
kindly advise next steps
run: 15.20-s038: (c) Copyright 1995-2017 Cadence Design Systems, Inc.
Top level design units:
top
ncelab: *W,DSEMEL: This SystemVerilog design will be simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
Loading snapshot worklib.top:sv … Done
SVSEED default: 1
ncsim: *W,DSEM2009: This SystemVerilog design is simulated as per IEEE 1800-2009 SystemVerilog simulation semantics. Use -disable_sem2009 option for turning off SV 2009 simulation semantics.
ncsim> source /incisiv/15.20/tools/inca/files/ncsimrc
ncsim> run
0
0
0
0
0
0
0
…
ncsim: *W,RNQUIE: Simulation is complete.
ncsim> exit
Done