Question related to inheritance and classes

SystemVerilog
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4

In reply to shubh2211:

I still don’t understand your question correctly, but here’s my interpretation :

You are given 3 handles, and you are asked to find out what the base classes for these handles are. (This looks like an assignment/interview question which doesn’t have actual code).

If this is UVM you can try calling “get_type_name” on the handles. That will give you the “extended classes”. As you already know the base classes for these “extended classes”, you have the answer.

If it’s not UVM but plain SV, you can use $typename to do the same.

Some sample code below :
With plain SV ::


class A;
endclass

class B extends A;
endclass

module test();
  A a=new();
  B b=new();
  
  initial begin
    $display("typename = %s", $typename(a));
    $display("typename = %s", $typename(b));
  end
endmodule

With UVM ::


import uvm_pkg::*;

class A extends uvm_object;
  `uvm_object_utils(A)

  function new(string name = "default");
    super.new(name);
  endfunction
endclass

class B extends A;
  `uvm_object_utils(B)

  function new(string name = "default");
    super.new(name);
  endfunction
  
endclass

module test();
  A a=new("base_class");
  B b=new("ext_class");
  
  initial begin
    $display("get_name = %s", a.get_name());
    $display("get_type_name = %s", a.get_type_name());
    $display("get_name = %s", b.get_name());
    $display("get_type_name = %s", b.get_type_name());
  end
endmodule