QuestaSim compile UVM library

UVM
1

Hello expert

I am a new guy for questasim, I want to use questasim to build UVM project, but I do not how to import UVM library,

I write 'include “uvm_pkg.sv” at the begin of .sv file, and I compile it, but I got a error message

** Error: (vlog-13053) D:/questasim/examples/test.sv(2): near “'i”: Illegal base specifier in numeric constant.
** Error: (vlog-13069) D:/questasim/examples/test.sv(2): near “'i”: syntax error, unexpected BASE, expecting class.

can you tell me why? and give me a manual for questasim?

Best Regards
Jack

2

In reply to JackShan:

You are getting syntax errors that are not likely anything to do with the particular tool you are using. You need to show us line 2 of test.sv and the lines before it.

And you want to import the uvm_pkg, not `include it. You might want to read SystemVerilog Coding Guidelines: Package import versus `include - Verification Horizons

3

In reply to dave_59:

infect，I just write one sentence until now

'include "uvm_pkg.sv"
4

In reply to JackShan:

until now, I just write very simple SystemVerilog sentence:


`include "uvm_pkg.sv" 
module hello_world_example; 
import uvm_pkg::*;  
`include "uvm_macros.svh" 
initial begin  
 `uvm_info("info1","Hello UVM!",UVM_LOW) 

end  
endmodule: hello_world_example

and I compile the code, then I got four errors

vlog -work work -vopt -sv -stats=none D:/questasim/examples/test.sv
QuestaSim-64 vlog 10.6c Compiler 2017.07 Jul 26 2017
** Error: D:/questasim/examples/test.sv(1): Cannot open include file "D:/questasim/ovm-2.1.2/../verilog_src/ovm-2.1.2/src/uvm_pkg.sv". -- Compiling module hello_world_example -- Importing package uvm_pkg (uvm-1.1d Built-in) ** Error: D:/questasim/examples/test.sv(4): Cannot open include file “D:/questasim/ovm-2.1.2/…/verilog_src/ovm-2.1.2/src/uvm_macros.svh”.
** Error: D:/questasim/examples/test.sv(6): (vlog-2163) Macro `uvm_info is undefined.
** Error: (vlog-13069) D:/questasim/examples/test.sv(6): near “(”: syntax error, unexpected ‘(’.

5

In reply to JackShan:

This related to your simulation/computer setup.
The path
D:/questasim/ovm-2.1.2/…/verilog_src/ovm-2.1.2
points to OVM and not UVM.
Please correct this and it will work.

6

In reply to chr_sue:

hello chr_sue

where can I modify the path? because I did not find setup in simulation column.

Best regards
Jack

7

In reply to JackShan:

You can set this with the environment variable UVM_HOME or you can modify your modelsim.ini file by setting
mtiUvm = $MODEL_TECH/…/uvm-1.1d or
mtiUvm = $MODEL_TECH/…/uvm-1.2

depending on which UVM version you want to run.

8

In reply to chr_sue:

I find following setting in file modelsim.ini

; ieee = $MODEL_TECH/../vital1995
;
; For compatiblity with previous releases, logical library name vital2000 maps
; to library vital2000 (a different library than library ieee, containing the
; same packages).
; A design should not reference VITAL from both the ieee library and the
; vital2000 library because the vital packages are effectively different.
; A design that references both the ieee and vital2000 libraries must have
; both logical names ieee and vital2000 mapped to the same library, either of
; these:
;   $MODEL_TECH/../ieee
;   $MODEL_TECH/../vital2000
;
verilog = $MODEL_TECH/../verilog
std_developerskit = $MODEL_TECH/../std_developerskit
synopsys = $MODEL_TECH/../synopsys
modelsim_lib = $MODEL_TECH/../modelsim_lib
sv_std = $MODEL_TECH/../sv_std
mtiAvm = $MODEL_TECH/../avm
mtiRnm = $MODEL_TECH/../rnm
mtiOvm = $MODEL_TECH/../ovm-2.1.2
mtiUvm = $MODEL_TECH/../uvm-1.1d
mtiUPF = $MODEL_TECH/../upf_lib
mtiPA  = $MODEL_TECH/../pa_lib
floatfixlib = $MODEL_TECH/../floatfixlib
mc2_lib = $MODEL_TECH/../mc2_lib
osvvm = $MODEL_TECH/../osvvm

So I just delete the sentence


mtiOvm = $MODEL_TECH/../ovm-2.1.2

it seems not ok, should I modified another place?

regards

9

In reply to JackShan:

What you see you should not modify.
The tool discussion is not allowed here in the public domain.
Please respond on my email:
christoph@christoph-suehnel.de