In reply to JackShan:
until now, I just write very simple SystemVerilog sentence:
`include "uvm_pkg.sv"
module hello_world_example;
import uvm_pkg::*;
`include "uvm_macros.svh"
initial begin
`uvm_info("info1","Hello UVM!",UVM_LOW)
end
endmodule: hello_world_example
and I compile the code, then I got four errors
vlog -work work -vopt -sv -stats=none D:/questasim/examples/test.sv
QuestaSim-64 vlog 10.6c Compiler 2017.07 Jul 26 2017
** Error: D:/questasim/examples/test.sv(1): Cannot open include file "D:/questasim/ovm-2.1.2/../verilog_src/ovm-2.1.2/src/uvm_pkg.sv". -- Compiling module hello_world_example -- Importing package uvm_pkg (uvm-1.1d Built-in) ** Error: D:/questasim/examples/test.sv(4): Cannot open include file “D:/questasim/ovm-2.1.2/…/verilog_src/ovm-2.1.2/src/uvm_macros.svh”.
** Error: D:/questasim/examples/test.sv(6): (vlog-2163) Macro `uvm_info is undefined.
** Error: (vlog-13069) D:/questasim/examples/test.sv(6): near “(”: syntax error, unexpected ‘(’.