Parameterized interface passing through uvm_config_db

UVM
,
1

for the following parameterize interface

interface intf_AB #(WIDTH = 31) (input bit clk); 
   logic           ack;
   logic           ready;
   logic           send; 
   logic [WIDTH:0] data;
...
endinterface

using the following config

uvm_config_db(virtual intf_AB#(n))::set(null,"uvm_test_top.*","vif",intf_AB);

but if the parameter is in a package

package param_pkg;
  parameter WIDTH=32;
endpackage


//
import param_pkg::*;
interface intf_AB  (input bit clk); 
   logic           ack;
   logic           ready;
   logic           send; 
   logic [WIDTH:0] data;
...
endinterface

how to use config_db to passing parameterize vif??
please help me out.

2

In reply to designer007:

Try using Scope Resolution Operator for parameter .


uvm_config_db(virtual intf_AB#( param_pkg:: WIDTH ))::set(null,"uvm_test_top.*","vif",intf_AB);
3

In reply to designer007:

Your interface is not parametrized so you can no longer create instance specific parameter overrides. You would just do

uvm_config_db(virtual intf_AB)::set(null,"uvm_test_top.*","vif",intf_AB);
4

In reply to dave_59:

dave, thanks for you relay

but I run a test as the following

//param_pkg.sv


package param_pkg;
	parameter n=8;
endpackage

//param_if.sv


import param_pkg::*;
interface param_if;
	logic [n-1:0] data;
	logic [n-1:0] addr;
endinterface

//top_tb.sv


module top_tb;

import uvm_pkg::*;
`include "uvm_macros.svh"
`include "param_if.sv"

param_if my_param_if();
dut dut_inst(
...);

initial begin
   uvm_config_db #(virtual param_if)::set(null, "uvm_test_top",                "vif", my_param_if);
run_test();
end

endmodule

//mycase0.sv


class my_case0 extends base_test;
   `uvm_component_utils(my_case0)
	virtual param_if param_if;

   function new(string name = "my_case0", uvm_component parent = null);
	//function new(string name, uvm_component parent);
      super.new(name,parent);
   endfunction 
   extern virtual function void build_phase(uvm_phase phase); 
   extern virtual function void connect_phase(uvm_phase phase); 

    task run_phase(uvm_phase phase);
	begin
               my_rst_seq my_seq= my_rst_seq::type_id::create("my_seq",this);
		phase.raise_objection(this,"rst_ctrl_seq active");
		my_seq.start(env.i_agt.m_sqr);
                 phase.drop_objection(this,"rst_ctrl_seq finished");

	end
endtask : run_phase	

endclass

function void my_case0::build_phase(uvm_phase phase);
   super.build_phase(phase);
       if(!uvm_config_db#(virtual param_if)::get(this,"","vif",param_if))
	`uvm_info("my_case0","error",UVM_MEDIUM)

endfunction

/////////////////////
I get the following error:

** Error: (vsim-13216) Illegal assignment to type ‘virtual param_if’ from type ‘interface param_if #()’: Vir. ‘param_if’ interface must be assigned a matching interface or virtual interface.

Time: 0 ps Iteration: 0 Instance: /top_tb File: ./top_tb.sv Line: 59

the simulator is questasim 64 2019.2_2

can you correct me, thanks!!!

5

In reply to designer007:

The code you show includes the definition of param_if inside the module top_tb. You should not be doing that. If you are also compiling param_if outride the module, that creates two different definitions. Also, where is line 59 and why is it showing #() if the interface is not parametrized?

6

In reply to dave_59:

thanks a lot, dave.

when I try


//include param_if out of top_tb ,it works fine
`include "param_if.sv"
module top_tb
....
endmoduel

or
//it works too
//not include param_if in top_tb file

vlog -timescale “10ps/10ps”
+incdir+./…
…/test_pkg.sv
./param_pkg.sv
./param_if.sv
./rst_agent_pkg.sv
./dut.sv
./top_tb.sv

But I still confused why it will be error with

** Error: (vsim-13216) Illegal assignment to type ‘virtual param_if’ from type ‘interface param_if #()’: Vir. ‘param_if’ interface must be assigned a matching interface or virtual interface.

Time: 0 ps Iteration: 0 Instance: /top_tb File: ./top_tb.sv Line: 59

it is very similar when you deal with parameterized interface.

Line 59:
uvm_config_db #(virtual param_if)::set(null, “uvm_test_top”, “vif”, my_param_if);

7

In reply to designer007:

This might be caused by your compile order and strategy. including package files is always a bad approach.
Could you please show how your data are packed and how do you compile it?

8

In reply to chr_sue:

here is the package


package rst_agent_pkg;
   `include "uvm_macros.svh"
   import uvm_pkg::*;
	 import test_pkg::*;
 
   `include "rst_item.sv"
   `include "rst_agent_cfg.sv"
   `include "rst_item_drv.sv"
   `include "rst_item_mon.sv"
   `include "rst_agent.sv"
   `include "seq_lib/rst_seq_lib.sv"
	 `include "rst_env.sv"
	 `include "base_test.sv"
	 `include "my_case0.sv"
//////////////	`include "rst_if.sv"
 
endpackage: rst_agent_pkg

////compile.do
quit -sim
rm -rf work
vlib work

vlog -timescale “10ps/10ps”
+incdir+./…
…/test_pkg.sv
./param_pkg.sv
./rst_agent_pkg.sv
./dut.sv
./top_tb.sv

vopt +acc top_tb dut -o opt

vsim
+UVM_TESTNAME=my_case0
+UVM_NO_RELNOTES
+UVM_TIMEOUT=100000000
-classdebug -uvmcontrol=all
opt

run 0

9

In reply to designer007:
Are you really importing the test_pkg to the rst_agent_pkg? Looks quite strange.
And I do not see the param_pkg. Where do you compile this package?

10

In reply to chr_sue:

sorry for confuse,
the original design is to test rst related design,
I just add some code to test the interface with param in pkg.
I compile param_pkg
in compile.do
////compile.do
quit -sim
rm -rf work
vlib work
vlog -timescale “10ps/10ps”
+incdir+./…
…/test_pkg.sv
*./param_pkg.sv *

11

In reply to designer007:
I believe your problem is here.
The param_pkg has to be compiled first because it is a package you are using in different places.
Afterwards you can compile the agent pkg and finally the test_pkg.
I have the impression you are not really familiar with the package approach.